EDA Spyglass

Spyglass

Spyglass

Posted by George Lin on May 17, 2025

https://www.bilibili.com/video/BV1cj411i7zf?spm_id_from=333.788.player.switch&vd_source=6bdb3504029acf6961e3195b9ad841b9

VC Spyglass 工具Lint检查默认使用的方法学说明位置

VC_STATIC_HOME/auxx/monet/tcl/GuideWare/soc/rtl_handoff/lint

VC_STATIC_HOME/auxx/monet/tcl/GuideWare/block/rtl_handoff/lint

VC Spyglass Lint检查时有哪些goal？

以block检查目标为例，有lint_rtl, lint_rtl_enhanced, lint_formal_aware_rtl, lint_dccompat, lint_formality等共10个默认的goal

Lint 各个goal主要检查内容是什么？

  • lint_rtl（默认使用）：连接性检查，动态仿真相关检查，不可综合结构检查，RTL结构性检查
  • lint_formal_aware_rtl:使用形式验证方法学对RTL进行lint检查，可进一步降低结果中的误报
  • lint_dccompat：RTL可实现性检查，包含了使用DC进行综合时对RTL的基本要求
  • lint_formality: 包含了使用formality等工具进行一致性比对时对RTL的基本要求

怎样在Lint检查时设置方法学要求以及检查目标集合？

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Spyglass中的跨复位域路径RDC问题

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Spyglass常见的合规与不合规的同步结构

CDC同步结构检查

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复位信号同步结构

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上图右图可以有效实现异步复位同步释放

Spyglass Qualifier声明示例

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层次化验证

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spyglass自动抽取block中顶层需要知道的东西

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SAM会向顶层屏蔽掉block中阴影部分的内容

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CDC Jitter流程

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看到CDC报了汇聚，则需要手动check是否做了格雷码转换之类的处理，CDC Jitter流程可以主动插入随机Jitter来模拟产生上述10这一中间态的场景。

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亮点是插入jitter的位置

可以通过tracediff看看插入不同jitter产生的动态仿真vcs波形是否有差别，从而自动判别。

CDC功能检查（即有了正确的结构，结构能否有正确的功能）

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功能性检查指Formal CDC Verification这一步

RDC约束

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RDC实例

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CDC合规同步路径的抓取

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CDC路径的时钟信息

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RTL级综合优化寄存器根源分析

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复位信号定义

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时钟关系检查

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Top Port的Reset

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TCM Timing Exception Confliction检查

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左右三栏中的左边两栏相互冲突

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Lint连接性检查

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如何在RDC中有效定义和约束Qualifier

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CATALOG
    FEATURED TAGS
    Synthesis Interconnect Protocol AMBA